Integrated circuits have become increasingly complex and heterogeneous. Modern circuit designs can include a variety of different components or resources including, but not limited to, registers, block Random Access Memory (RAM), multipliers, processors, and the like. This increasing complexity makes placement of components as well as the routing of signals within a circuit design more cumbersome.
Circuitry within components may have asymmetric propagation or processing delays for different inputs. That is, a signal at one input pin may have a substantially different propagation delay to the component output than a signal at another of the input pins. The throughput of the component is determined by the signal having the largest overall delay from component input to output. As a consequence, the processing time required by the component is increased when late arriving signals are assigned to pins having large processing delays. By reordering assignment of signals to pins during pin placement, pins having large processing delays can be matched with early arriving signals to reduce the longest delay, which dictates the overall delay of the component.
Previous analysis and placement methods sort signals by arrival time and pins by processing delay. Signals with the earliest arrival are assigned to pins having the longest processing delay. In doing so, the time in which output becomes available can be improved. However, this method of assignment may not yield optimal results in some cases. One or more embodiments may address one or more of the above issues.